1. Field of the Invention
The present invention relates to circuitry used for interfacing different families of logic circuits, and more particularly, to an emitter coupled logic (ECL) to bipolar complementary metal oxide semiconductor (BiCMOS) and complementary metal oxide semiconductor (CMOS) translator.
2. Description of the Related Art
Situations often arise where certain portions of a digital system require high-speed logic gates while other portions of the system can tolerate low-speed logic gates. In these situations, it is advantageous to use more than one logic family because, where low-speed can be tolerated, a low-speed family such as CMOS will dissipate less power than a high-speed family such as ECL.
When more than one logic family is used in a system, it is necessary to take into account the fact that the output of one family may not be compatible with the input of another. In order to properly transfer data between different logic families, special interfacing circuits, or "translators," can be used to convert the logic signals generated by one family into signals which can be understood by a different family.
FIG. 1 illustrates a block diagram of a conventional ECL-to-CMOS translator 20. The translator 20 converts ECL level signals to CMOS level signals. During operation, an ECL level signal is received at node 22. The dynamic signal range for ECL logic is about -1.7 to -1.4 Volts for logical low ("0") and about -0.9 to -0.8 Volts for logical high ("1"). An ECL receiver circuit 24 converts the received ECL signal to a pair of differential ECL level signals (i.e., complementary ECL signals). The differential ECL signals are carried by lines 26 and 28 to a translator circuit 30. The translator circuit 30 converts the differential ECL level signals to a single CMOS level signal. The single CMOS level signal is output at node 32. The dynamic signal range for CMOS logic is about -5.0 to -4.8 Volts for logical low ("0") and about -0.4 to 0.0 Volts for logical high ("1").
FIG. 2 illustrates a circuit implementation of the conventional ECL-to-CMOS translator 20 of FIG. 1. The ECL receiver circuit 24 is basically a current-mode logic (CML) gate, and its operation is well known in the art. Specifically, bipolar transistor Q1, which receives the ECL input signal at its base, is connected in emitter follower configuration to a voltage-comparator circuit which is constructed from bipolar transistors Q2 and Q3 and resistors R1 and R2. Voltage comparator circuits are the basic components of ECL and CML gates. Lines 26 and 28, which carry the pair of differential ECL signals, are connected to the collectors of transistors Q3 and Q2, respectively.
The translator circuit 30 includes p-channel MOSFET transistors MP1 through MP3, n-channel MOSFET transistors MN1 through MN5, and bipolar transistors Q4 and Q5. Transistor Q4 has its collector connected to a first voltage source which supplies a voltage roughly equal to that of a CMOS logical high, i.e., about 0.0 Volts. Transistor Q5 has its emitter connected to a second voltage source which supplies a voltage roughly equal to that of a CMOS logical low, i.e., about -5.2 Volts. The emitter of transistor Q4 and the collector of transistor Q5 are connected together and form output node 32.
Translator circuit 30 generates CMOS level signals on output node 32 by switching only one of transistors Q4 and Q5 on at a time. When transistor Q4 is switched on, transistor Q5 is off, and output node 32 is pulled up to a CMOS logical high, i.e., about -0.4 Volts. When transistor Q5 is switched on, transistor Q4 is off, and output node 32 is pulled down to a CMOS logical low, i.e., about -4.8 Volts.
The pair of differential ECL signals are received at the gates of transistors MP1 and MP2 via lines 26 and 28, respectively. Transistors MP1 through MP3 and MN1 through MN5, in response to the differential ECL signals, switch transistors Q4 and Q5 on and off. Specifically, when line 26 carries a low signal, and line 28 carries a high signal, transistor MP1 switches on and transistor MP2 switches off. Because transistor MP1 is on, transistor MN2 switches on and causes the gates of transistors MP3, MN3, and MN4 to be pulled low. Transistor MP3 switches on and causes the base of transistor Q4 to be pulled high, thus, switching transistor Q4 on. Because transistor Q4 is on, a high signal is received at the gate of transistor MN5 which switches transistor MN5 on. The base of transistor Q5 is pulled low which switches transistor Q5 off.
conversely, when line 26 carries a high signal, and line 28 carries a low signal, transistor MP1 switches off and transistor MP2 switches on. Because transistor MP2 is on, the gates of transistors MP3, MN3 and MN4 are pulled high. Transistor MN3 switches on which pulls the base of transistor Q4 low, thus, switching transistor Q4 off. Transistor MN5 remains off which permits transistor Q5 to switch on.
The conventional ECL-to-CMOS translator 20 of FIGS. 1 and 2 has a number of deficiencies. First, due to the large number of transistors employed, the translator 20 tends to dissipate a large amount of power. Second, the large number of transistors require a period of time to complete the switching operation, which is too slow for many modern applications. Finally, the large number of transistors makes the circuit impractical for modern high density products; there are often space and layout problems which render the manufacture of the circuit economically unfeasible.
Thus, there is a need for an ECL-to-CMOS translator which dissipates less power, has fewer components, and has higher speed than conventional translators.